In data processing systems, data signals may be input into a central processor from multiple sources. In such systems it is necessary to synchronize the transfer of data with respect to a common clock, referred to as a master local oscillator. In some instances, it may be desirable or expedient to locate a data source remotely with respect to the central processor and local clock. Any time that such a system is operated synchronously and the remote data source is separated from the local clock by an unknown distance, the phase of the returning data relative to the local clock is shifted because of the transmission delay induced by the physical length of the signal conductors. The phase shift of the data signal relative to the local clock can be great enough in some instances to cause a violation of the set-up and hold time requirements of local logic circuits.
In some low-frequency circuits, the phase variation of data bits relative to a local clock oscillator is not significant, especially for short-run cable installations. However, as the frequency of data transfer increases, and in particular if cable lengths between remote and local circuits are great enough or are subject to conditions which induce phase variations, means are required for maintaining the clock frequency of the remote data source tied to the frequency of the local clock, with provisions for insuring that the data is clocked by the local clock within a specified window such that bit errors do not occur due to violation of set-up time and hold time specifications of local logic circuits.
The foregoing considerations are particularly critical when a flip-flop is used to retime data. In such an operation, there is a certain period of time during which the data signal must remain stable relative to the rising clock edge input to establish an accurately retimed output. For instance, the data signal must have assumed a logic one value for a certain amount of time prior to the onset of the clock rising edge and must maintain the logic one value and not transition to a logic zero for a certain period of time after the rising clock signal has achieved logic one value. This range of time with respect to the rising clock edge is referred to as the "not allowed time". The foregoing clock/data timing constraints must be observed to obtain a valid data synchronization so that the output data signal is a faithful and accurate representation of the input data signal.